In the field of data communications, data terminal equipment (DTE) is the source or destination of data in a communication connection. The DTE is typically connected to data communication equipment (DCE), which is in turn connected to the communication channel. The DTE may be a dumb terminal or printer, however in most modern communication networks, the DTE is typically a computer, a bridge, or a router, which interconnects local area networks (LANs).
DCEs are typically modems or other types of communication devices. The DCE resides between the DTE and a communication channel. The DCE provides a connection for the DTE to send and receive data to and from the communication channel. Additionally, the DCE provides clocking to the DTE. In an analog communication network, such as a plain old telephone service (POTS) network, the DCE is typically a modem. In a digital communication network, such as a frame relay network, the DCE is typically a CSU/DSU (channel service unit/data service unit).
DTE and DCE interfaces are defined by the physical layer in the OSI (Open Systems Interconnection) model. The most common standards for DTE/DCE devices are EIA (Electronic Industries Association) RS-232-C and RS-232-D. Outside the United States, these standards are the same as the V.24 standard of the CCITT. Other DTE/DCE standards include the EIA RS-366-A, as well as the CCITT X.20, X.21, and V.35 standards. The later standards are used for high-speed communication over telephone lines.
As noted, clocking is provided by the DCE to the DTE. The DCE sends a clocking signal to the DTE, and the DTE responds by sending data synchronously with the clocking signal. Theoretically, there is perfect timing between the clocking signal transmitted by the DCE and the synchronous data signal transmitted by the DTE. In practice, however, there is some delay before the DTE data signal is transmitted. This delay is attributable to such factors as the physical proximity of the DCE and the DTE, the length of the cable connecting the DCE and the DTE, and temperature changes in the system.
FIG. 1 is a schematic view illustrating a typical prior art communication environment 5 in which a DTE 12 is interfaced to a communication channel 11 by a DCE 13. In the communication environment 5 illustrated in FIG. 1, the DCE 13 employs a typical prior art clocking circuit. A clock source 18 generates a timing signal (DCE ST), which is sent from the DCE 13 to the DTE 12 on connection 15. In response to signal DCE ST, the DTE 12 sends a data signal (DTE SD) to the DCE 13 on connection 16. The DCE 13 samples signal DTE SD in data latch 17. A clocking signal (SD LATCH CLK) is also provided by clock source 18 to data latch 17 on connection 14. The SD LATCH CLK signal is used to clock the sampling of signal DTE SD in data latch 17.
As illustrated in FIG. 1, in prior art systems the same clocking signal is typically used for signal DCE ST and signal SD LATCH CLK. However, in most installations connections 15 and 16 typically are much longer than connection 14. Thus, signals DCE ST and DTE SD typically are required to traverse much greater physical distances than signal SD LATCH CLK. As a result, signal DTE SD may be delayed in reaching data latch 17 relative to signal SD LATCH CLK. Temperature changes in the system may also result in varying delays.
Because data is sampled by the DCE 13 at clock transitions, if delays in the system become significant compared to the frequency of the data signal, data clocking errors may occur as follows: the DCE 13 may double sample the data, or the DCE 13 may miss sampling the data altogether. Such errors are more likely to occur as the data rate increases. This is especially troublesome as network designers strive for higher and higher data rates.
FIG. 2 is a graphical illustration of the DCE ST, DTE SD, and SD LATCH CLK signals of the communication environment 5 of FIG. 1. Signal DTE SD is sampled in data latch 17 (of FIG. 1) on the rising edge of the SD LATCH CLK signal. System delays, such as those discussed above, can cause data latch 17 to sample signal DTE SD at a transition in signal DTE SD. The sampling point for this condition is illustrated in FIG. 2 by reference numeral 19.
With reference back to FIG. 1, the effects of the above-described delay may be alleviated in some instances by sending signal SD LATCH CLK from the DCE 13 to the DTE 12 and having DTE 12 return signal SD LATCH CLK back to DCE 13. The DCE 13 then uses the returned clock signal (rather than the original clock signal) to sample the data. In this way, the time delay between the clock signal used for sampling and the DTE data signal is minimized. This type of timing scheme is typically referred to as terminal timing.
When the DTE does not have terminal timing capability, another way of addressing delay errors is by manually inverting the phase of the DCE's internal clock (i.e., signal SD LATCH CLK on connection 14 of FIG. 1) relative to the clock provided to the DTE (i.e., signal DCE ST on connection 15 of FIG. 1), so that signal DTE SD is sampled in the middle of the DCE's internal clock cycle rather than at a transition point. However, the efficacy of this method depends on the amount of delay in the system, which may differ depending on the specific installation. Each site must be evaluated and the manual inversion must be done on a site by site basis during installation, depending on the configuration of each site. However, post-installation changes in the DTE cable, in the DTE itself, or elsewhere in the system, can cause changes in the amount of delay present in the system. In such cases, subsequent manual intervention is required to adjust the clock phase.
Thus, there is a need in the industry for a circuit and method that detect clocking errors between DCEs and DTEs, and dynamically adjust the clock phase to eliminate such errors.